This application claims the benefit of Korean Patent Application No. 2000-40005, filed Jul. 12, 2000 in Korea, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to an active-matrix liquid crystal display (LCD) device and a method of fabricating the same, and more particularly, to an array substrate having thin film transistors (TFTs) for the active-matrix LCD device and the method of fabricating the array substrate.
2. Discussion of the Related Art
A LCD device makes use of optical anisotropy to display images. A typical LCD device includes an upper substrate, a lower substrate, and a liquid crystal material interposed therebetween.
FIG. 1 is an exploded perspective view showing a typical LCD device 11 including an upper substrate 5 and an opposing lower substrate 22 and a liquid crystal layer 14 interposed therebetween. The upper substrate 5 and the lower substrates 22 are alternatively called a color filter substrate and an array substrate, respectively. On the upper substrate 5, a black matrix 6 and a color filter layer 7 that includes a plurality of sub-color-filters red (R), green (G), and blue (B) are formed. The black matrix 6 surrounds each sub-color-filter, thereby forming an array matrix. Further on the upper substrate 5, a common electrode 18 is formed to cover the color filter layer 7 and the black matrix 6.
On the lower substrate 22 opposing the upper substrate 5, a thin film transistor (TFT) xe2x80x9cTxe2x80x9d is formed to function a switching element in the shape of an array matrix corresponding to the color filter layer 7. In addition, a plurality of crossing gate lines 13 and data lines 15 are positioned such that the TFT xe2x80x9cTxe2x80x9d is located proximate to each crossing portion of the gate line 13 and the data line 15. The crossing gate line 15 and the data line 15 define a pixel region xe2x80x9cPxe2x80x9d. In the pixel region xe2x80x9cPxe2x80x9d, a pixel electrode 17 is disposed and is made of a transparent conductive material, usually indium tin oxide (ITO), for example.
Liquid crystal molecules of the liquid crystal layer 14 are aligned in accordance with electric signals applied by the TFT xe2x80x9cTxe2x80x9d, thereby controlling transmission of incident rays of light to form a display image. Specifically, the gate line 13 and the data line 15 apply electric signals to a gate electrode and a source electrode of the TFT xe2x80x9cT,xe2x80x9d respectively. The signal applied to the drain electrode is transmitted to the pixel electrode 17 in order to align the liquid crystal molecules of the liquid crystal layer 14. Subsequently, rays of backlight (not shown) selectively pass through the liquid crystal layer 14 such that an image is displayed. A fabricating process of the array substrate requires repeated steps of deposition, photolithography, etching, and stripping for various layers.
In practice, an inverted staggered type TFT is widely deployed due to its simplicity and high quality and can be classified as either a back-channel-etch type or an etching-stopper type, based on the method of forming a channel. The etch-stopper type TFT is alternatively referred to as a channel-passivated type, because it further includes a channel passivation layer that protects the channel of the TFT. More processes are required for fabricating the etch-stopper type TFT because of the channel passivation layer. However, the channel passivation layer effectively decreases passage of electrons across the channel, thereby improving operational quality. In addition, because the channel passivation layer protects the channel from being over-etched during fabrication, generation of defects within the channel is prevented.
FIG. 2 shows an array substrate of a liquid crystal display device implementing a conventional inverted staggered type TFT. As shown, the array substrate 22 includes a pixel region xe2x80x9cPxe2x80x9d defined by crossing gate line 13 and data line 15, and includes a TFT xe2x80x9cTxe2x80x9d, a pixel electrode 17, and a storage capacitor xe2x80x9cC.xe2x80x9d The TFT xe2x80x9cTxe2x80x9d includes a gate electrode 26, a source electrode 28, a drain electrode 30, and an active layer 55. An island-shaped channel passivation layer 57 is disposed upon the active layer 55, and is made of an insulating material. The source electrode 28 electrically connects with the data line 15, the gate electrode 26 electrically connects with the gate line 13, and the pixel electrode 17 directly contacts the drain electrode 30.
Referring now to FIGS. 3A to 6A and 3B to 6B, a method for fabricating the conventional array substrate will now be explained. FIGS. 3A to 6A are sequential plan views showing the array substrate during the fabrication process, and FIGS. 3B to 6B are cross-sectional views taken along a line xe2x80x9cIIIxe2x80x94IIIxe2x80x9d of FIG. 2. FIGS. 3B to 6B correspond to FIGS. 3A to 6A, respectively.
In FIGS. 3A and 3B, a surface of a substrate 22 is cleaned to remove particles and/or contaminants. Then, a first metal layer is deposited upon the substrate 22 using a sputtering process, for example, and is subsequently patterned using a first mask to integrally form a gate electrode 26 and a gate line 13. At this point, a portion of the gate line 13 is used as a first capacitor electrode 13a of the storage capacitor xe2x80x9cCxe2x80x9d shown in FIG. 2. Aluminum (Al) is widely used as the material with which to form the gate electrode 26 for decreasing RC delay. However, pure aluminum is chemically weak and may result in the formation of hillocks during high-temperature processing. Accordingly, instead of pure aluminum, aluminum alloys or layered aluminum structures are used to form the gate electrode. As mentioned above, the gate electrode 26 and the first capacitor electrode 13a are usually made of the same metal layer as the gate line 13. After the first metal layer is patterned, a gate insulating layer 50 is formed to cover the first metal layer. Then, an amorphous silicon layer (a-Si:H) 55 and an insulating layer 57 are sequentially formed upon the gate insulating layer 50.
In FIGS. 4A and 4B, the insulating layer 57 is patterned to form an island-shaped channel passivation layer 57a disposed over the gate electrode 26. Then, a doped amorphous silicon is deposited upon the channel passivation layer 57a and the amorphous silicon layer 55 (in FIG. 3B). The doped amorphous silicon layer and the amorphous silicon layer are patterned together to form an island-shaped ohmic contact layer 58 and an active layer 55a with the channel passivation layer 57a interposed therebetween.
Thereafter, as shown in FIGS. 5A and 5B, a second metal layer is deposited upon the array substrate 22 and subsequently patterned to form a data line 15, a source electrode 28, and a drain electrode 30. The data line 15 crosses with the gate line 13 to define a pixel region xe2x80x9cP.xe2x80x9d The source electrode 28 and the drain electrode 30 are spaced apart from each other and formed to overlap the gate electrode 26 with the active layer 55a interposed therebetween.
As shown in FIGS. 6A and 6B, a transparent conductive material is deposited upon the array substrate 22 and subsequently patterned to form a pixel electrode 17 disposed in the pixel region xe2x80x9cP.xe2x80x9d The transparent conductive material is preferably selected from a group including at least indium tin oxide (ITO) and indium zinc oxide (IZO), for example. The pixel electrode 17 electrically contacts the drain electrode 30 at a drain edge portion xe2x80x9cDxe2x80x9d and a portion of the pixel electrode 17 overlaps the first capacitor electrode 13a and functions as a second capacitor electrode 17a. The first capacitor electrode 13a and the second capacitor electrode 17a compose the storage capacitor xe2x80x9cC.xe2x80x9d Thereafter, a passivation layer 60 is formed to cover an entire surface of the array substrate 22 having the pixel electrode 17.
During the above fabrication processes, the pixel electrode 17 is usually patterned using a wet etching method. However, when an etchant is used for patterning the pixel electrode 17, the etchant may abnormally penetrate along a boundary line xe2x80x9cExe2x80x9d (in FIG. 6A) between the pixel electrode 17 and the drain electrode 30. Accordingly, the etchant over-etches the pixel electrode 17 along the boundary line xe2x80x9cExe2x80x9d (in FIG. 6A) such that the pixel electrode 17 is electrically separated from the drain electrode 30, thereby creating a point defect within a display area of the LCD device.
Accordingly, the present invention is directed to a method of fabricating an LCD device that substantially obviates one or more of problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide an improved method of fabricating an array substrate for an LCD device such that an open-line defect between a pixel electrode and a drain electrode is prevented.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, an array substrate of a liquid crystal display device includes a substrate, a gate line including a gate electrode disposed on the substrate along a first direction, a data line disposed on the substrate along a second direction, a barrier disposed on the substrate and spaced apart from the gate electrode and the data line, a gate insulating layer disposed on the substrate, the gate line, the gate electrode, and the barrier, an active layer disposed on the gate insulating layer over the gate electrode, a source electrode disposed on the active layer, a drain electrode having a first portion disposed on the active layer opposite to the source electrode, and a second portion disposed on the insulating layer crossing over the barrier; a pixel region defined by a cross of the gate line and the data line, and a pixel electrode electrically connected to the second portion of the drain electrode.
In another aspect, the present invention provides a method of fabricating an array substrate for a liquid crystal display device. The method includes the steps of forming a first metal layer including a gate line, a gate electrode, and a barrier upon a substrate, wherein the barrier is spaced apart from the gate electrode, forming a gate insulating layer to cover the first metal layer, forming an amorphous silicon layer upon the gate insulating layer, forming a doped amorphous silicon layer upon the amorphous silicon layer, forming both an island-shaped active layer from the amorphous silicon layer and an island-shaped ohmic contact layer from the doped amorphous silicon layer that are disposed over the gate electrode, forming a second metal layer including a data line, a source electrode, and a drain electrode, the drain electrode having a first portion disposed upon the ohmic contact layer and a second portion disposed upon the gate insulating layer and over the barrier, and forming a pixel electrode to overlap the second portion of the drain electrode such that the pixel electrode electrically contacts the drain electrode.
In another aspect, the present invention provides a liquid crystal display device including a thin film transistor formed upon a substrate, the thin film transistor including a source electrode, a drain electrode, an active layer, and a gate electrode, and at least one barrier formed upon the substrate beneath the drain electrode, wherein the barrier is disposed between an end portion of the drain electrode and an end portion of the active layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.